Failure analysis of a semiconductor device is done with a variety of techniques used to locate, analyze, and identify faults in the device. The semiconductor integrated circuit (IC) or chip is typically formed on a silicon substrate using a layering technique which results in a multilayered device composed of various layers of metal, polysilicon, dielectric and other materials. Many ICs are fabricated at once on a wafer. After fabricating the wafer, failure analysis is performed to detect and isolate failures in the IC while the ICs or chips are still part of the wafer.
Typical failure techniques used on the front side of the wafer include mechanical probing, electron beam probing, photo emission microscopy, and optical beam induced current (“OBIC”). The wafer is positioned at a testing station and power probes are placed on the front surface of the wafer to power up the selected IC on the wafer and make that IC at least partially operative. The failure analysis techniques are then used on the front surface of the wafer to detect and isolate faults in the IC. Some optical failure analysis techniques, such as emission microscopy and OBIC, are also performed on the back side of the wafer. Typically, the wafer is inverted before the power probes are placed on the surface of the wafer, before optical failure analysis techniques are used on the backside of the wafer to detect and isolate faults in the IC.
Photo emission microscopy is a “hot spot” detection technique which detects photons emitted from faults in the IC. The type of faults which typically generate a photo emission include junction defects, contact spiking, hot electrons, latch-up, poly filaments, and substrate damage and contamination. The photo emissions are the result of electron-hole recombinations which generate light primarily in the infrared region of the light spectrum. The photo emissions are transmitted through semi-transparent dielectric layers, polysilicon layers, and passivation layers, and emerge from the front side of the wafer where they may be seen by viewing the front side of the wafer. The photo emissions are also transmitted through the substrate of the wafer and emerge from the back side of the wafer where they may be seen by viewing the back side of the wafer.
In photo emission microscopy, an infrared optical microscopic device or other infrared optical viewing device, such as a charge coupled device (CCD) camera with a monitor, is used to obtain an image of the photo emissions from the back side of the wafer. The photo emission image is overlaid on a bright field reference image of the IC to isolate and identify the fault sites associated with the photo emissions. Power must be supplied to the device in the photo emission microscopy technique. The power is supplied to the device by placing power probes on the semiconductor wafer and connecting the power probes to an external power source when performing the failure analysis.
The OBIC technique is another optical failure technique which detects photo emissions. The OBIC technique uses a laser scanning microscope with an infrared laser for backside wafer analysis. The laser induces electron-hole pairs in the silicon which quickly recombine in most instances. However, when electron-hole pairs are induced near a p-n junction, the electrons are swept across the diffusion region forming a current flow at the p-n junction. A current amplifier connected to a side of the p-n junction amplifies the current to produce a visual image of the current flow on a video monitor. The laser scanning microscope also produces a bright field image of the device from laser light reflected from the device. The current flow image and bright field image are simultaneously displayed on the monitor to isolate and identify where current is flowing in the device. The points of current flow in the device are then analyzed for faults and defects. Power may be supplied to the device in the OBIC technique to bias the device. However, the OBIC technique will produce an image regardless of whether the device is biased. Power is supplied to the device by placing power probes on the semiconductor wafer and connecting the power probes to an external power source when performing the failure analysis.
The effectiveness of optical failure analysis techniques used on the front side of the wafer is diminished because of the increased complexity of many ICs. In particular, ICs are being manufactured with additional metal interconnect layers. The increasing number of layers makes photo emission microscopy from the front side of the wafer difficult, if not impossible, because of the lack of visibility of the photo emissions from the front side of the wafer. The additional metal interconnect layers include as many as six upper layers for power busses, high density signal routing lines, and bond pads. The metal interconnect layers are placed above the substrate of the wafer where active devices are formed. The active devices are generally the source of most faults detectable using optical failure analysis techniques on the front side of the wafer. The photons emitted from the fault cannot pass through the numerous opaque metal interconnection layers of the device. Instead, the photon emissions pass between or are scattered around the metal interconnection layers, preventing the detection of photo emissions from the surface of the wafer or otherwise decreasing the accuracy of locating the fault. The effectiveness of the optical failure analysis techniques used on the front side of the wafer is diminished because the additional metal interconnect layers obstruct the visibility of faults in the active devices. However, optical photo emission microscopy can be effectively used on the back side of the wafer where it is less likely that faults are obstructed by metal interconnection layers.
Application of the failure analysis techniques on the back side of the wafer is complicated with existing wafer probing techniques. Typically, the wafer is inverted and placed in the probing fixture of the testing station and beneath an emission microscope or an infrared sensitive CCD camera. Probes are then placed on the semiconductor device after the semiconductor is inverted, and electrical connections are made to the probes. The process of contacting the probes to the semiconductor device typically involves viewing the surface of the inverted wafer on a video monitor while mechanically manipulating the probes to place the probe tips on connection points formed on the surface of the wafer. This process is complicated in terms of eye-to-hand coordination since the video image is a reverse image of the wafer from the viewpoint of a normal viewing. Also, the equipment operator must view the wafer surface indirectly though the video monitor rather than viewing the wafer surface directly while placing the probes on the wafer. The process of connecting the probes to the semiconductor device is generally time consuming and prone to error.
Application of the failure analysis techniques on the front side of the wafer is also complicated with existing wafer probing techniques. Probes are typically placed on the front side of the wafer by contacting tips of probes to very small signal pads or connection points on the front side of the IC the front surface of the wafer through a microscope. The probes have a relatively long, cantilevered-like arm which extend from micrometer-like devices used to adjust the mechanical position of the tips of the probes. Because of the relatively long arm of the probes and their cantilevered extension from the adjustment mechanism, the movement of the tip of the probes is magnified, which makes placement of the probe tip very difficult, tedious and time-consuming to precisely and accurately position the probe tip on the desired connection point of the IC. Moreover, the probe tip is also subject to natural environmental because of the magnification effect of the relatively long arm of the probe. Consequently, connecting the probes to the semiconductor device for front side failure analysis techniques is generally time consuming and prone to error.
It is with respect to these and other considerations that have given rise to the present invention.